Intel Presents Its Process and Packaging Innovation Roadmap To 2025

Intel Corporation today revealed one of the most detailed process and packaging technology roadmaps the company has ever provided, showcasing a series of foundational innovations that will power products through 2025 and beyond. In addition to announcing RibbonFET, its first new transistor architecture in more than a decade, and PowerVia, an industry-first new backside power delivery method, the company highlighted its planned swift adoption of next-generation extreme ultraviolet lithography (EUV), referred to as High Numerical Aperture (High NA) EUV. Intel is positioned to receive the first High NA EUV production tool in the industry.

Intel Corporation today revealed one of the most detailed process and packaging technology roadmaps the company has ever provided, showcasing a series of foundational innovations that will power products through 2025 and beyond. In addition to announcing RibbonFET, its first new transistor architecture in more than a decade, and PowerVia, an industry-first new backside power delivery method, the company highlighted its planned swift adoption of next-generation extreme ultraviolet lithography (EUV), referred to as High Numerical Aperture (High NA) EUV. Intel is positioned to receive the first High NA EUV production tool in the industry.

“Building on Intel’s unquestioned leadership in advanced packaging, we are accelerating our innovation roadmap to ensure we are on a clear path to process performance leadership by 2025,” Intel CEO Pat Gelsinger said during the global “Intel Accelerated” webcast. “We are leveraging our unparalleled pipeline of innovation to deliver technology advances from the transistor up to the system level. Until the periodic table is exhausted, we will be relentless in our pursuit of Moore’s Law and our path to innovate with the magic of silicon.”

«The industry has long recognized that the traditional naming of nanometer-based process nodes no longer matches the 1997 true length metric,» the company said in a statement. “Today, Intel introduced a new naming structure for its compute nodes, creating a clear and consistent framework to provide customers with a more accurate view across the industry. This clarity is more important than ever with the launch of Intel Manufacturing Services (IFS). ”

Gelsinger promised that «the innovations unveiled today will not only enable the company’s product roadmap, but will also be critical to our manufacturing services customers.» And he assured: «A lot of interest has been shown in IFS and I am happy that today we announced our first two important clients.»

Intel specialists outlined the following roadmap with the new node names and the innovations that enable each case:

⦁ Intel 7 offers a performance per watt increase of approximately 10% to 15% over Intel 10nm SuperFin based on FinFET transistor optimizations. Intel 7 will be included in products such as Alder Lake for customers in 2021 and Sapphire Rapids for the data center, which is expected to be in production in the first quarter of 2022.

⦁ Intel 4 fully adopts EUV lithography to print incredibly small features with ultra-short wavelength light. With an increase in performance per watt of approximately 20%, as well as area improvements, Intel 4 will be ready and in production by the second half of 2022 on products to be delivered in 2023, including Meteor Lake for customers and Granite Rapids for centers. data.

⦁ Intel 3 takes further advantage of FinFET optimizations and a higher EUV to deliver an approximately 18% performance-per-watt increase over Intel 4, along with additional area improvements. Intel 3 will be ready to go into production in products during the second half of 2023.

⦁ Intel 20A ushers in the angstrom era with two innovative technologies: RibbonFET and PowerVia. RibbonFET, Intel’s implementation of a wrap-around gate transistor will be the company’s first new transistor architecture since pioneering FinFETs in 2011, delivering faster transistor switching speeds, while achieving the same impulse current as multiples. fins in a smaller space. PowerVia is Intel’s first implementation in the back-end power delivery industry that optimizes the transmission signal by eliminating the need for power routing at the front of the wafer. Intel 20A is expected to be ready in 2024. The company is also excited about the opportunity to partner with Qualcomm using its Intel 20A process technology.

⦁ Starting in 2025: Beyond the Intel 20A, the Intel 18A is already in development and is anticipated to launch in early 2025 with enhancements to the RibbonFET that will provide another major leap in transistor performance. Intel is also working to define, build, and implement next-generation Alta NA EUV, and expects to receive the industry’s first production tool for Alta NA EUV. Intel has a close alliance with ASML to ensure the success of this industry breakthrough beyond the current generation of EUV.

«Intel has a long history of fundamental process innovations that are driving the industry by leaps and bounds,» said Dr. Ann Kelleher, senior vice president and general manager, Technology Development. “We led the transition to deformed silicon at 90nm, High-k metal gates at 45nm and FinFET at 22nm. Intel 20A will be another watershed moment in process technology with two game-changing innovations: RibbonFET and PowerVia. »

Dra. Ann Kelleher, Senior Vice President and General Manager of Intel Technology Development.

Intel announced that AWS will be the first customer to use IFS packaging solutions, while providing the following insights on the company’s industry-leading advanced packaging roadmap:

⦁ EMIB continues to lead the industry as the first 2.5D Integrated Bridge solution, with product shipments since 2017. Sapphire Rapids will be Xeon’s first data center product to ship in high volume with EMIB (Multi-Array Integrated Interconnect Bridge). ). It will also be the industry’s first dual-reticle-sized device to deliver nearly the same performance as a monolithic design. In addition to Sapphire Rapids, the next generation EMIB will go from a 55 micron bump pitch to 45 microns.
⦁ Foveros leverages wafer-level packaging capabilities to offer a one-of-a-kind 3D stacking solution. Meteor Lake will be Foveros’ second-generation implementation in a customer product, and features a 36-micron bump pitch, mosaics spanning multiple technology nodes, and a thermal design power range of 5 to 125W.
⦁ Foveros Omni ushers in the next generation of Foveros technology by offering unlimited flexibility with performance 3D stacking technology for modular and matrix-to-matrix interconnect designs. Foveros Omni enables die unbundling by mixing multiple top die tiles with multiple base tiles in mixed fabrication nodes and is expected to be ready for volume fabrication in 2023.
⦁ Foveros Direct switches to direct copper-to-copper bonding for low resistance interconnects and blurs the boundary between where the wafer ends and where the packaging begins. Foveros Direct enables bump pitches of less than 10 microns that will deliver an order of magnitude increase in interconnect density for 3D stacking, opening up new concepts for functional partitioning of arrays that were previously unattainable. Foveros Direct is complementary to Foveros Omni and is also expected to be ready in 2023.

The company closed its webcast with the confirmation of more details about its Intel InnovatiON event, which will be held in a hybrid format; in-person in San Francisco and online, October 27-28, 2021.